This invention is generally related to sense amplifiers and more particularly to techniques for improving their sensitivity.
Sense amplifiers are used in digital solid state integrated circuit (IC) applications which require low voltage sensing. They can be used in memory read circuits for memory bit sensing, in bus signal receivers, and for interfacing low voltage data paths in a processor. Typically, the sense amplifiers are formed in the same IC die as the memory storage array and the processor data paths, using digital logic fabrication processes such as complimentary metal oxide semiconductor (CMOS). Although its inputs may be considered to be analog, the outputs of a sense amplifier are full swing voltages that are digital, i.e. one of only two stable DC levels which are essentially that of the power supply and power return node voltages.
A conventional CMOS sense amplifier at its input has a source coupled matched differential pair, an active load such as a regenerative circuit to provide a full swing, and a current sink or source. As the dimensions of the constituent field effect transistors (FETs) of the input pair decrease, it has been observed that variations in the threshold voltage Vt of the input FETs among different manufactured units have increased. This leads to increased offset voltages in the input pair and the active load, which reduces the sensitivity of the sense amplifier.